1. Field of the Invention
The present invention relates generally to an epitaxial process, and more specifically to an epitaxial process that forms two different epitaxial layers beside two gates.
2. Description of the Prior Art
For decades, chip manufacturers have made metal-oxide-semiconductor (MOS) transistors faster by making them smaller. As the semiconductor processes advance to very deep sub micron era, such as 65-nm node or beyond, how to increase the driving current in MOS transistors has become a critical issue. In order to improve the device performances, crystal strain technology has been developed. Crystal strain technology is becoming more and more attractive as a means for getting better performance in the field of MOS transistor fabrication. Putting a strain on a semiconductor crystal alters the speed at which charges move through that crystal. Strain makes MOS transistors work better by enabling electrical charges, such as electrons, to pass more easily through the silicon lattice of the gate channel.
In the known art, attempts have been made to use a strained silicon layer, which has been grown epitaxially on a silicon substrate with a silicon germanium (SiGe) epitaxial layer or a silicon carbide (SiC) epitaxial layer disposed in between. In this type of MOS transistor, a biaxial compressive or tensile strain is induced in the epitaxy silicon layer due to the silicon germanium or silicon carbide having a larger or smaller lattice constant than silicon, and, as a result, the band structure is altered, and the carrier mobility increases. This enhances the speed performances of the MOS transistors.